1. Technical Field
The present invention relates in general to circuitry enabling transmission of high frequency signals through a connection, while simultaneously providing a DC path from the connection to an attached circuit with the high frequency AC signals to the attached circuit blocked. More particularly, the present invention relates to providing a high fidelity “loop-back” connection for transmission of self-test signals between two interconnected integrated circuit (IC) terminals while simultaneously providing a low frequency or DC path back to a tester used to test ICs on a wafer.
2. Related Art
Test systems to test integrated circuits on a wafer during production typically include a probe card containing spring probes for contacting IC pads on the wafer. The spring probes are supported on a substrate with routing lines included in the substrate to electrically connect the spring probes to a tester. The test signals provided from the tester typically are provided at a low frequency.
Sometimes ICs include high frequency circuits that are interconnected, or “looped-back” at the IC pads for self-test. The self-test signals are typically provided at a high frequency relative to test system signals. Interconnecting two such pads through a loop-back in a test system, thus, may not be practical because the high frequency signals cannot be provided through the test system.
Directly connecting the pads of the IC by hard wiring a connection to provide the “loop-back” without providing a path for test system signals, may not allow some necessary low frequency tests of the interconnection to be performed. A hard wired connection between IC pads with a separate connection to the test system may also not be practical because the high frequency signals provided through the IC interconnect line may adversely affect the test system.
FIG. 1 shows a block diagram of a test system using a probe card for testing Devices Under Test (DUTs) containing ICs on a semiconductor wafer. The test system includes a tester made up of a test controller 4 connected by a communication cable 6 to a test head 8. The test system further includes a prober 10 made up of a stage 12 for mounting a wafer 14 being tested, the stage 12 being movable to contact the wafer 14 with probes 16 on a probe card 18. The prober 10 includes the probe card 18 supporting probes 16 which contact DUTs formed on the wafer 14.
In the test system, test data is generated by the test controller 4 of the tester and transmitted through the communication cable 6, test head 8, probe card 18, probes 16 and ultimately to DUTs on the wafer 14. Test results are then provided from DUTs on the wafer back through the probe card 18 to the test head 8 for transmission back to the test controller 4. Once testing is complete, the wafer 14 is diced up to separate the DUTs.
Test data provided from the test controller 4 is divided into the individual tester channels provided through the cable 6 and separated in the test head 8 so that each channel is carried to a separate one of the probes 16. The channels from the test head 8 are linked by connectors 24 to the probe card 18. The probe card 18 then links each channel to a separate one of the probes 16.
FIG. 2 shows a cross sectional view of the probe head portion 20 of a typical probe card 18. Besides the probe head 20, a typical probe card 18 also typically includes components for mechanically supporting the probe head 20 relative to the wafer 14, and for electrically connecting the probe card 18 to the flexible cable connectors 24 of the test system that are not shown in FIG. 2.
The probe head 20 is made up of a space transformer substrate 22 that contains traces 26 to distribute or “space transform” signals from a Land Grid Array (LGA) made up of pads 32 provided on a first side 28 of the substrate 22 to spring probes 16 provided on the opposing second side 30. The signals from the connectors 24 are distributed to pads 32 forming the LGA. The space transformer substrate 22 is typically constructed from either multi-layered ceramic or multi-layered organic based laminates, effectively forming a Printed Circuit Board (PCB). The traces 26 are formed on one or more internal layers of the multi-layer substrate 22 and are interconnected by vias, such as via 23. The traces 26 typically include signal lines as well as power and ground lines. The power supply lines may be distributed on a separate layer of the substrate 22 from signal lines and separated by a ground plane to prevent signal interference. The space transformer substrate 22 with embedded circuitry, probes and LGA is referred to as the probe head 20.
Although shown with LGA pads 32 forming connections on the space transformer substrate 22, connection can be made to internal lines 26 using a further transmission line trace 34. The line 34 can be connected by a via to internal layers 26 of the space transformer substrate 22, or directly connected by a via through the substrate 22 to a spring probe 16.
The substrate 22 is shown in FIG. 2 forming the probe head 20 of the probe card 18, and providing space-transformation from pads 32 to match the routing pitch of probes 16, but a typical probe card 18 can include one or more additional PCBs. An additional PCB can provide further routing on internal layers to provide added space-transformation as design space requirements may dictate.
The pads 32 forming the LGA can be connected by a number of types of connectors either directly to the test head connectors 24, or through one or more additional PCB layers to the connectors 24. The connectors used for such an interconnection may include stamped or formed spring elements, pogo pins, ZIF flexible cable connectors, non-ZIF flexible cable connectors, conductive elastomer bumps, directly soldered wires, or other connectors as design constraints may require.